This application advances the non-local spin-FET, or Polaron, first disclosed in U.S. Pat. No. 8,748,957, entitled COHERENT SPIN FIELD EFFECT TRANSISTOR. Specifically, that application discloses a non-local spin-FET made possible by the deposition of graphene on an oxide like cobalt oxide, grown over a metal such as cobalt. Application of a magnetic field alters electron mobility across the graphene field at room temperature and above, in an easily manufacturable design that is integrable with Si-CMOS design, but offers lower power and smaller size requirements. The technologically manufacturable, scalable development, operable at room temperature offers a solution to impending limitations in conventional Si-CMOS transistors.
The subject matter of this patent application was developed without federal or state funding. Although the inventor named herein is the beneficiary of support from various organizations, and is employed by a University, no University or time, compensation or apparatus was employed, involved or relied on in the development of the subject matter disclosed and claimed herein. Similarly, no funding or materials or apparatus provided by any organization was used in the development of this technology.
The non-local spin valve or spin field effect transistor of U.S. Pat. No. 8,748,957 relies on the provision of a magnetically polarizable, electrically insulating or semiconducting surface on which graphene may be directly deposited. The electrically insulating or semiconducting surface is preferably an oxide. The oxide is formed on a ferromagnetic substrate. Polarization will result in polarization of the metal ions of the oxide dielectric at both top and bottom surfaces, which in turn leads to polarization of the graphene valence/conduction band electrons. Application of appropriate magnetically polarizable source and drain electrodes provides a high on-off rate spin-FET.
Cobalt is an exemplary ferromagnetic base as disclosed in U.S. Pat. No. 8,748,957. Electrically polarizable cobalt oxide, an insulating oxide, is readily formed on the cobalt base, and a thin film (2-3 monolayers or ML) of graphene is readily formed on the oxide, through any of a variety of methods, including preferably molecular beam epitaxy (MBE). Other processes, such as atomic layer deposition (ALD), or CVD, PVD and enhanced plasma deposition followed by annealing may be employed. Whether the annealing is practiced with the deposition of carbon, or subsequently, a continuous, protective layer of graphene is formed. In this respect, the device is distinct from devices prepared by the formation of graphene films on other substrates, like a conductor like copper, and then physically transferred to the underlying layer, which introduces edge and boundary defects as well as defects due to twisting. Graphene is also formed from high temperature “cracking” of SiC but those temperatures are not consistent with the preparation of the devices of this invention, nor integration with Si-CMOS technology.
As an alternative to cobalt oxide (substantially all Co3O4) U.S. Pat. No. 8,748,957 discloses the use of chrome oxide in place of cobalt oxide as the insulating body or layer on which the graphene is deposited. It further discloses, in the alternative, to provide a cobalt oxide or chrome oxide (chromia) “top gate” or gate formed over the graphene. The provision of chromia (Cr2O3) is of value in that it provides a mechanism for making the coherent spin-FET voltage switchable, reducing power requirements and improving performance at room temperatures and above. There are other magneto-electric material possibilities, but chromia would provide the voltage switching capability readily. Thin films in particular are thought to best facilitate voltage controlled switching of polarization at the interface (on-off effect).
Research suggests that providing graphene on chromia, or chromia top gates on graphene, may not be straightforward, however. Catalytic destruction of graphitic carbon by chromia, or chromia formation, has been observed. The chrome oxide catalyzed degradation (oxidation) of a variety of carbon based compounds is well documented Pradier et al., Appl. Catal. B: Env. 27, 73 (2000). Whether the chromia is deposited on the graphene, or graphene formation on the chromia is attempted, the graphene layer formed is incomplete and destruction through catalytic chromia occurs rapidly at T>800° K. Accordingly, it remains an object of those of skill in this art to find a way to provide magnetic tunnel junctions and coherent spin-FETS of the type first disclosed in U.S. Pat. No. 8,748,957 in a voltage-switchable embodiment without damage to the graphene layer.
Specifically, complete oxidation of deposited chromia is achieved at temperatures at or above 700-750° C. Kaspar et al, Surface Science, 618, 159-166 (2013). Yet, chromia catalytically etches/oxidizes graphene at temperatures above 800 K. Thus, whether graphene is formed on a chromia support, and annealed at UHV, or a stable graphene layer is formed and chromia is deposited in the form of a “top gate” the intimate formation of chromia and graphene presents process issues. Careful control and staging of these formation steps would appear necessary, and may be difficult to incorporate in scalable production and to integrate with conventional Si-CMOS (complementary metal oxide semiconductor) technology.